diff --git a/board/flexibity/dataflash/Makefile b/board/flexibity/dataflash/Makefile new file mode 100644 index 0000000..e0162ca --- /dev/null +++ b/board/flexibity/dataflash/Makefile @@ -0,0 +1,118 @@ +# TODO: set this appropriately for your local toolchain +ifndef ERASE_FCT +ERASE_FCT=rm -f +endif +ifndef CROSS_COMPILE +CROSS_COMPILE=arm-elf- +endif + +TOOLCHAIN=gcc + +BOOTSTRAP_PATH=../../.. + +# DataFlashBoot Configuration for Flexibity + +# Target name (case sensitive!!!) +TARGET=FLEXIBITY +# Board name (case sensitive!!!) +BOARD=flexibity +# Link Address and Top_of_Memory +LINK_ADDR=0x200000 +TOP_OF_MEMORY=0x301000 +# Name of current directory +PROJECT=dataflash + +ifndef BOOT_NAME +BOOT_NAME=$(PROJECT)_$(BOARD) +endif + +INCL=./$(BOOTSTRAP_PATH)/board/$(BOARD)/$(PROJECT) + +ifeq ($(TOOLCHAIN), gcc) + +AS=$(CROSS_COMPILE)gcc +CC=$(CROSS_COMPILE)gcc +LD=$(CROSS_COMPILE)gcc +NM= $(CROSS_COMPILE)nm +SIZE=$(CROSS_COMPILE)size +OBJCOPY=$(CROSS_COMPILE)objcopy +OBJDUMP=$(CROSS_COMPILE)objdump +CCFLAGS=-g -mcpu=arm926ej-s -Os -Wall -D$(TARGET) -I$(INCL) +ASFLAGS=-g -mcpu=arm926ej-s -c -Os -Wall -D$(TARGET) -I$(INCL) -DTOP_OF_MEM=$(TOP_OF_MEMORY) + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS+=-nostartfiles -nostdlib -Wl,-Map=$(BOOT_NAME).map,--cref +LDFLAGS+=-T $(BOOTSTRAP_PATH)/elf32-littlearm.lds -Ttext $(LINK_ADDR) +OBJS=crt0_gnu.o + +endif + +OBJS+=\ + $(BOARD).o \ + main.o \ + gpio.o \ + pmc.o \ + debug.o \ + sdramc.o \ + dataflash.o \ + _udivsi3.o \ + _umodsi3.o \ + div0.o \ + udiv.o \ + string.o + +rebuild: clean all + +all: $(BOOT_NAME) + +ifeq ($(TOOLCHAIN), gcc) +$(BOOT_NAME): $(OBJS) + $(LD) $(LDFLAGS) -n -o $(BOOT_NAME).elf $(OBJS) + $(OBJCOPY) --strip-debug --strip-unneeded $(BOOT_NAME).elf -O binary $(BOOT_NAME).bin +endif + + +$(BOARD).o: $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c -o $(BOARD).o + +main.o: $(BOOTSTRAP_PATH)/main.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/main.c -o main.o + +gpio.o: $(BOOTSTRAP_PATH)/driver/gpio.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/gpio.c -o gpio.o + +pmc.o: $(BOOTSTRAP_PATH)/driver/pmc.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/pmc.c -o pmc.o + +debug.o: $(BOOTSTRAP_PATH)/driver/debug.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/debug.c -o debug.o + +sdramc.o: $(BOOTSTRAP_PATH)/driver/sdramc.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/sdramc.c -o sdramc.o + +dataflash.o: $(BOOTSTRAP_PATH)/driver/dataflash.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/dataflash.c -o dataflash.o + +crt0_gnu.o: $(BOOTSTRAP_PATH)/crt0_gnu.S + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/crt0_gnu.S -o crt0_gnu.o + +div0.o: $(BOOTSTRAP_PATH)/lib/div0.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/div0.c -o div0.o + +string.o: $(BOOTSTRAP_PATH)/lib/string.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/string.c -o string.o + +udiv.o: $(BOOTSTRAP_PATH)/lib/udiv.c + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/udiv.c -o udiv.o + +_udivsi3.o: $(BOOTSTRAP_PATH)/lib/_udivsi3.S + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_udivsi3.S -o _udivsi3.o + +_umodsi3.o: $(BOOTSTRAP_PATH)/lib/_umodsi3.S + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_umodsi3.S -o _umodsi3.o + +clean: + $(ERASE_FCT) *.o *.bin *.elf *.map diff --git a/board/flexibity/dataflash/flexibity.h b/board/flexibity/dataflash/flexibity.h new file mode 100644 index 0000000..26dc9c8 --- /dev/null +++ b/board/flexibity/dataflash/flexibity.h @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Flexibity + * Copyright (c) 2006, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * File Name : flexibity.h + * Object : + * Creation : May 3rd 2011 + *----------------------------------------------------------------------------- + */ +#ifndef _FLEXIBITY_H +#define _FLEXIBITY_H + +/* ******************************************************************* */ +/* PMC Settings */ +/* */ +/* The main oscillator is enabled as soon as possible in the c_startup */ +/* and MCK is switched on the main oscillator. */ +/* PLL initialization is done later in the hw_init() function */ +/* ******************************************************************* */ +#if 0 +#define MASTER_CLOCK (119999465/2) /* 120MHz */ +#define MASTER_CLOCK (179999198/2) /* 180MHz */ +#endif +#define MASTER_CLOCK (198656000/2) /* 198.656MHz */ +#define PLL_LOCK_TIMEOUT 1000000 + +#if 0 +#define PLLA_SETTINGS 0x2125BF2d /* 120MHz */ +#define PLLA_SETTINGS 0x2125BF1E /* 180MHz */ +#endif +#define PLLA_SETTINGS 0x2060BF09 /* 198.656MHz */ +#define PLLB_SETTINGS 0x10483F0E + +/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ +#define MCKR_SETTINGS (AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2) +#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS) + +/* ******************************************************************* */ +/* DataFlash Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_BASE_SPI AT91C_BASE_SPI0 +#define AT91C_ID_SPI AT91C_ID_SPI0 + +/* SPI CLOCK */ +#define AT91C_SPI_CLK 33000000 +/* AC characteristics */ +/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ +#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ + +#define DF_CS_SETTINGS (AT91C_SPI_NCPHA | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) + + +/* ******************************************************************* */ +/* BootStrap Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_SPI_PCS_DATAFLASH AT91C_SPI_PCS1_DATAFLASH /* Boot on SPI NCS0 */ + +#define IMG_ADDRESS 0x8400 /* Image Address in DataFlash */ +#define IMG_SIZE 0x33900 /* Image Size in DataFlash */ + +#define MACH_TYPE 0xB95 /* Flexibity */ +#define JUMP_ADDR 0x23F00000 /* Final Jump Address */ + +/* ******************************************************************* */ +/* Application Settings */ +/* ******************************************************************* */ +#define CFG_DEBUG +#define CFG_DATAFLASH +#define CFG_SDRAM +#define CFG_HW_INIT +#undef CFG_MEMTEST /* Can enable 1 test at a time due to 4K limitation */ +#undef CFG_MEMTEST_DATA +#undef CFG_MEMTEST_ADDR +#undef CFG_MEMTEST_DEVICE + +#endif /* _AT91SAM9260EK_H */ + diff --git a/board/flexibity/flexibity.c b/board/flexibity/flexibity.c new file mode 100644 index 0000000..3767e95 --- /dev/null +++ b/board/flexibity/flexibity.c @@ -0,0 +1,522 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Flexibity + * Copyright (c) 2006, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * File Name : flexibity.c + * Object : + * Creation : May 3rd 2011 + *----------------------------------------------------------------------------- + */ +#include "../../include/part.h" +#include "../../include/gpio.h" +#include "../../include/pmc.h" +#include "../../include/debug.h" +#include "../../include/sdramc.h" +#include "../../include/main.h" +#ifdef CFG_DATAFLASH +#include "../../include/dataflash.h" +#endif + +#ifdef CFG_MEMTEST +/* + * Memory test routines are from: + * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C + */ +typedef unsigned int datum; /* Set the data bus width to 32 bits. */ +#define BASE_ADDRESS ((volatile datum *) 0x20000000) +#define NUM_BYTES (64*1024*1024) +#define NULL (0x0) + +#ifdef CFG_MEMTEST_DATA +datum memTestDataBus(volatile datum * address); +#endif +#ifdef CFG_MEMTEST_ADDR +datum * memTestAddressBus(volatile datum * baseAddress, unsigned long nBytes); +#endif +#ifdef CFG_MEMTEST_DEVICE +datum * memTestDevice(volatile datum * baseAddress, unsigned long nBytes); +#endif + +#endif /* CFG_MEMTEST */ + +static inline unsigned int get_cp15(void) +{ + unsigned int value; + __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value)); + return value; +} + +static inline void set_cp15(unsigned int value) +{ + __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value)); +} + +#ifdef CFG_HW_INIT +/*----------------------------------------------------------------------------*/ +/* \fn hw_init */ +/* \brief This function performs very low level HW initialization */ +/* This function is invoked as soon as possible during the c_startup */ +/* The bss segment must be initialized */ +/*----------------------------------------------------------------------------*/ +void hw_init(void) +{ + unsigned int cp15; + + /* Configure PIOs */ + const struct pio_desc hw_pio[] = { +#ifdef CFG_DEBUG + {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A}, +#endif + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + /* Disable watchdog */ + writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); + + /* At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC */ + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); + + /* PCK = PLLA = 2 * MCK */ + pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); + /* Switch MCK on PLLA output */ + pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); + + /* Configure PLLB */ + pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); + + /* Configure CP15 */ + cp15 = get_cp15(); + cp15 |= I_CACHE; + /* cp15 &= ~I_CACHE; */ + set_cp15(cp15); + + /* Configure the PIO controller */ + pio_setup(hw_pio); + + /* Configure the EBI Slave Slot Cycle to 64 */ + writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3)); + +#ifdef CFG_DEBUG + /* Enable Debug messages on the DBGU */ + dbg_init(BAUDRATE(MASTER_CLOCK, 115200)); + + dbg_print("Flexibity AT91Bootstrap...\n\r"); +#endif /* CFG_DEBUG */ + +#ifdef CFG_SDRAM + /* Initialize the matrix */ + writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA); + /* Configure SDRAM Controller */ +#if 1 + /* CLK=10ns, MCLK=99.328MHz */ + /* TWR = tDPL = 2 2CLK always */ + /* TRC = tRC = 65ns = 7 clk */ + /* TRP = tRP = 20ns = 2 clk */ + /* TRCD = tRCD = 20ns = 2 clk */ + /* TRAS = tRAS = 45ns = 5 clk */ + /* ? TXSR = tRRC = 65ns = 8 clk */ + /* Refresh = 64ms = 6400 clk */ + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_13 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | + AT91C_SDRAMC_TRC_7 | + AT91C_SDRAMC_TRP_2 | + AT91C_SDRAMC_TRCD_2 | + AT91C_SDRAMC_TRAS_5 | + AT91C_SDRAMC_TXSR_8, /* Control Register */ + 645, /* Refresh Timer Register */ + AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ +#endif +#if 0 + /* CLK= 16ns, MCLK=60MHz (does not start u-boot) */ + /* TWR = tDPL = 2 2CLK always */ + /* TRC = tRC = 65ns = 4 clk */ + /* TRP = tRP = 20ns = 2 clk */ + /* TRCD = tRCD = 20ns = 2 clk */ + /* TRAS = tRAS = 45ns = 3 clk */ + /* TXSR = tRRC = 65ns = 4 clk */ + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_13 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | + AT91C_SDRAMC_TRC_4 | + AT91C_SDRAMC_TRP_2 | + AT91C_SDRAMC_TRCD_2 | + AT91C_SDRAMC_TRAS_3 | /* *5 */ + AT91C_SDRAMC_TXSR_4, /* *8 */ /* Control Register */ + 1032, /* Refresh Timer Register */ + AT91C_SDRAMC_MD_SDRAM); +#endif +#if 0 + /* CLK= 11ns, MCLK=90MHz */ + /* TWR = tDPL = 2 2CLK always */ + /* TRC = tRC = 65ns = 6 clk */ + /* TRP = tRP = 20ns = 2 clk */ + /* TRCD = tRCD = 20ns = 2 clk */ + /* TRAS = tRAS = 45ns = 5 clk */ + /* TXSR = tRRC = 65ns = 6 clk */ + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_13 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | + AT91C_SDRAMC_TRC_6 | /* *7 */ + AT91C_SDRAMC_TRP_2 | + AT91C_SDRAMC_TRCD_2 | + AT91C_SDRAMC_TRAS_5 | /* *5 */ + AT91C_SDRAMC_TXSR_6, /* *8 */ /* Control Register */ + 710, /* Refresh Timer Register */ + AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ +#endif +#endif /* CFG_SDRAM */ +#ifdef CFG_MEMTEST +#ifdef CFG_MEMTEST_DATA + if (memTestDataBus(BASE_ADDRESS) != 0) { + dbg_print("Data bus test failed!\n\r"); + } + dbg_print("Data bus test passed.\n\r"); +#endif +#ifdef CFG_MEMTEST_ADDR + if (memTestAddressBus(BASE_ADDRESS, NUM_BYTES) != NULL) { + dbg_print("Address bus test failed!\n\r"); + } + dbg_print("Address bus test passed.\n\r"); +#endif +#ifdef CFG_MEMTEST_DEVICE + if (memTestDevice(BASE_ADDRESS, NUM_BYTES) != NULL) { + dbg_print("Memory device test failed!\n\r"); + } + dbg_print("Memory device test passed.\n\r"); +#endif +#endif /* CFG_MEMTEST */ +} +#endif /* CFG_HW_INIT */ + +#ifdef CFG_SDRAM +/*------------------------------------------------------------------------------*/ +/* \fn sdramc_hw_init */ +/* \brief This function performs SDRAMC HW initialization */ +/*------------------------------------------------------------------------------*/ +void sdramc_hw_init(void) +{ + /* Configure PIOs */ +/* const struct pio_desc sdramc_pio[] = { + {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; +*/ + /* Configure the SDRAMC PIO controller to output PCK0 */ +/* pio_setup(sdramc_pio); */ + + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0)); + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0)); + +} +#endif /* CFG_SDRAM */ + +#ifdef CFG_DATAFLASH + +/*------------------------------------------------------------------------------*/ +/* \fn df_recovery */ +/* \brief This function erases DataFlash Page 0 if BP4 is pressed */ +/* during boot sequence */ +/*------------------------------------------------------------------------------*/ +void df_recovery(AT91PS_DF pDf) +{ +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH) + /* Configure PIOs */ + const struct pio_desc bp4_pio[] = { + {"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT}, + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + /* Configure the PIO controller */ + writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC); + pio_setup(bp4_pio); + + /* If BP4 is pressed during Boot sequence */ + /* Erase NandFlash block 0*/ + if ( !pio_get_value(AT91C_PIN_PA(31)) ) + df_page_erase(pDf, 0); +#endif +} + +/*------------------------------------------------------------------------------*/ +/* \fn df_hw_init */ +/* \brief This function performs DataFlash HW initialization */ +/*------------------------------------------------------------------------------*/ +void df_hw_init(void) +{ + /* Configure PIOs */ + const struct pio_desc df_pio[] = { + {"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A}, +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH) + {"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A}, +#endif +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH) + {"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B}, +#endif + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }; + + /* Configure the PIO controller */ + pio_setup(df_pio); +} +#endif /* CFG_DATAFLASH */ + +#ifdef CFG_MEMTEST +#ifdef CFG_MEMTEST_DATA +/********************************************************************** + * + * Function: memTestDataBus() + * + * Description: Test the data bus wiring in a memory region by + * performing a walking 1's test at a fixed address + * within that region. The address (and hence the + * memory region) is selected by the caller. + * + * Notes: + * + * Returns: 0 if the test succeeds. + * A non-zero result is the first pattern that failed. + * + **********************************************************************/ +datum +memTestDataBus(volatile datum * address) +{ + datum pattern; + + + /* + * Perform a walking 1's test at the given address. + */ + for (pattern = 1; pattern != 0; pattern <<= 1) + { + /* + * Write the test pattern. + */ + *address = pattern; + + /* + * Read it back (immediately is okay for this test). + */ + if (*address != pattern) + { + return (pattern); + } + } + + return (0); + +} /* memTestDataBus() */ +#endif +#ifdef CFG_MEMTEST_ADDR +/********************************************************************** + * + * Function: memTestAddressBus() + * + * Description: Test the address bus wiring in a memory region by + * performing a walking 1's test on the relevant bits + * of the address and checking for aliasing. This test + * will find single-bit address failures such as stuck + * -high, stuck-low, and shorted pins. The base address + * and size of the region are selected by the caller. + * + * Notes: For best results, the selected base address should + * have enough LSB 0's to guarantee single address bit + * changes. For example, to test a 64-Kbyte region, + * select a base address on a 64-Kbyte boundary. Also, + * select the region size as a power-of-two--if at all + * possible. + * + * Returns: NULL if the test succeeds. + * A non-zero result is the first address at which an + * aliasing problem was uncovered. By examining the + * contents of memory, it may be possible to gather + * additional information about the problem. + * + **********************************************************************/ +datum * +memTestAddressBus(volatile datum * baseAddress, unsigned long nBytes) +{ + unsigned long addressMask = (nBytes/sizeof(datum) - 1); + unsigned long offset; + unsigned long testOffset; + + datum pattern = (datum) 0xAAAAAAAA; + datum antipattern = (datum) 0x55555555; + + + /* + * Write the default pattern at each of the power-of-two offsets. + */ + for (offset = 1; (offset & addressMask) != 0; offset <<= 1) + { + baseAddress[offset] = pattern; + } + + /* + * Check for address bits stuck high. + */ + testOffset = 0; + baseAddress[testOffset] = antipattern; + + for (offset = 1; (offset & addressMask) != 0; offset <<= 1) + { + if (baseAddress[offset] != pattern) + { + return ((datum *) &baseAddress[offset]); + } + } + + baseAddress[testOffset] = pattern; + + /* + * Check for address bits stuck low or shorted. + */ + for (testOffset = 1; (testOffset & addressMask) != 0; testOffset <<= 1) + { + baseAddress[testOffset] = antipattern; + + if (baseAddress[0] != pattern) + { + return ((datum *) &baseAddress[testOffset]); + } + + for (offset = 1; (offset & addressMask) != 0; offset <<= 1) + { + if ((baseAddress[offset] != pattern) && (offset != testOffset)) + { + return ((datum *) &baseAddress[testOffset]); + } + } + + baseAddress[testOffset] = pattern; + } + + return (NULL); + +} /* memTestAddressBus() */ +#endif +#ifdef CFG_MEMTEST_DEVICE +/********************************************************************** + * + * Function: memTestDevice() + * + * Description: Test the integrity of a physical memory device by + * performing an increment/decrement test over the + * entire region. In the process every storage bit + * in the device is tested as a zero and a one. The + * base address and the size of the region are + * selected by the caller. + * + * Notes: + * + * Returns: NULL if the test succeeds. + * + * A non-zero result is the first address at which an + * incorrect value was read back. By examining the + * contents of memory, it may be possible to gather + * additional information about the problem. + * + **********************************************************************/ +datum * +memTestDevice(volatile datum * baseAddress, unsigned long nBytes) +{ + unsigned long offset; + unsigned long nWords = nBytes / sizeof(datum); + + datum pattern; + datum antipattern; + + + /* + * Fill memory with a known pattern. + */ + for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++) + { + baseAddress[offset] = pattern; + } + + /* + * Check each location and invert it for the second pass. + */ + for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++) + { + if (baseAddress[offset] != pattern) + { + return ((datum *) &baseAddress[offset]); + } + + antipattern = ~pattern; + baseAddress[offset] = antipattern; + } + + /* + * Check each location for the inverted pattern and zero it. + */ + for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++) + { + antipattern = ~pattern; + if (baseAddress[offset] != antipattern) + { + return ((datum *) &baseAddress[offset]); + } + } + + return (NULL); + +} /* memTestDevice() */ +#endif +#endif /* CFG_MEMTEST */ + diff --git a/include/part.h b/include/part.h index 8fa55fb..b1ff38d 100644 --- a/include/part.h +++ b/include/part.h @@ -33,6 +33,11 @@ #ifndef _PART_H #define _PART_H +#ifdef FLEXIBITY +#include "AT91SAM9260_inc.h" +#include "flexibity.h" +#endif + #ifdef AT91SAM9260 #include "AT91SAM9260_inc.h" #include "at91sam9260ek.h"